– From the above description, it becomes obvious that the AD7–AD0lines are serving a dual purposeand that they need to be demultiplexed to get all the information.
– The high order bitsof the address remain on the bus for three clock periods. However, the low order bitsremain for only one clock periodand they would be lost if they are not saved externally. Also, notice that the low order bitsof the address disappearwhen they are needed most.
– To make sure we have the entire address for the full three clock cycles, we will use an external latchto save the value of AD7–AD0 when it is carrying the address bits. We use the ALEsignal to enable this latch.
– Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7–AD0 lines can be used for their purpose as the bi-directional data lines.
• The high order address is placed on the address bus and hold for 3 clk periods,
• The low order address is lost after the first clk period, this address needs to be hold however we need to use latch
• The address AD7 –AD0 is connected as inputs to the latch 74LS373.
• The ALE signal is connected to the enable (G) pin of the latch and the OC –Output control –of the latch is grounded